Register File Synthesis in ASIP Design

A Retargetable Compiler of VLIW ASIP for Media Signal Processing

In the last decade extensive researches have been carried out in ASIP (Application Specific Instruction Processor) design field. One of the key steps in ASIP design is code generation by a retargetable compiler. In this paper we describe our experience in implementing a retargetable compiler for VLIW ASIP based on ORC (Open Research Compiler) framework. Orienting towards a new register file acc...

Exploring Register File and Memory Organization in Asip Synthesis

An Application Specific Instruction Set Processor (ASIP) is a processor designed for one particular application or for a set of specific applications. An ASIP exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements. A typical ASIP design flow includes key steps such as application analysis, design space exploration, instruction s...

A Power Aware Cache and Register File Design Space Exploration

Application-Specific Instruction Sets Processor with Implicit Registers to Improve Register Bandwidth

Application-Specific Instruction (ASI ) set Processors (ASIP) have become an important design choice for embedded systems due to runtime flexibility, which cannot be provided by custom ASIC solutions. One major bottleneck in maximizing ASIP performance is the limitation on the data bandwidth between the General Purpose Register File (GPRF) and ASIs. This paper presents the Implicit Registers (I...

Object-Oriented ASIP Design and Synthesis

SystemC-Plus from the ODETTE project provides the ability to simulate and synthesise object-oriented specifications into hardware. The current ODETTE compiler translates each object instance into a finite state machine; this effectively duplicates (modulo dead code removal) in hardware the methods of a class for each of its instances. We describe an alternative synthesis approach which parallel...